PRINCIPAL ENGINEER, DIGITAL DESIGN ENGINEERING

As a member of our team, you will have the opportunity to.
Lead and support digital design work from RTL to GDSII; Be a key member of the Digital local team to drive the architectures of new products and/or key digital modules under his/her responsibility.
Decomposing system-level requirements to a set of requirements and specifications at the digital hardware level; Studying the new top-edge power IC specifications and developing the design (and relative documentation) for one or more digital modules and/or top-level; Developing Verilog/System Verilog RTL code.
Performing coding rules and conformance checks; Improving the quality of RTL, scripting, tools and propose new realistic ideas which can reduce the time to market in a reasonable and short amount of time; Work with digital and analog verification teams on verification plans, test cases, and analyzing test results; Develop a test (on a UVM-based environment and/or Formal) for the designed RTL module/modules and verify it.
If necessary, develop a digital model of analog blocks, verification IPs or a script to automate some phases of the verification flow; Modelling/simulating/debugging digital circuits.
Simulate in both DMS and AMS verification environment.
Implement the RTL into a new generation FPGA family for testing and debugging; Work in close collaboration with the back-end team to define the floorplan strategy to meet the stringent timing and area requirements.
Liaising/mentoring the physical design team to achieve implementation of the digital cores; Participate to the evaluation of the fabricated IC in our measurement lab; The successful candidate will work closely with other cross-functional teams to define, implement, and introduce products to our customers.
Teams include business, applications, product definition, product engineering, layout, test engineering, project management, CAD/EDA, etc.; Mentor junior engineers, and not only, to develop high quality standard RTL; Work within the overall ADI digital design community to proliferate & share best practice methodologies and technologies; Animate design reviews; Write documentation in accordance with company QA policy.
Required Skills/Experience.
MSEE degree in Electronics Engineering with 10+ years relevant hands-on experience in chip-level and circuit-level architecture definition, RTL design and verification; Solid background in digital electronic and signal processing; Experience in lead the architecture and specification of complex digital systems; Working experience in RTL design, synthesis, Verilog/System Verilog/VHDL languages; Deep knowledge of RTL coding techniques and good design practices; Have a very good vision of the entire digital IC design flow from RTL to GDSII; Working experiences in digital IC project and technical leader role; Good understanding of physical and digital implementation (i.
., from synthesis, LEC, P&R, scan insertion, static timing analysis, etc.…); Working experience with Cadence and Synopsys RTL design flow is highly recommended; Familiarity with Linux and version control systems (Perforce/Git/SVN); Knowledge of at least one scripting language such as Python/TCL/Perl/bash; Effective analytical and problem-solving skills; Ability to manage multiple tasks concurrently; Good attitude, ability to collaborate, strong motivation, desire to learn new things, and team player; Good verbal and written presentation/communication and organization skills; Ability to work in multifunctional teams; Fluent English (oral and written).
“Nice to have” Qualifications.
Experience with power management IC development; Experience with mixed-signal verification techniques (UVM/Formal); Experience in mentoring junior engineers; Understanding of digital design flows and associated tools.